August 27, 2008
Home > Events > Hsin-Chu, Taiwan

Agenda and Registration!

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Agenda
9:00-10:00
 Breakfast / Vendor Fair / Workshop / Registration
10:00-10:40
Keynote by Wally Rhines: A Demographic Driven Design Evolution
10:40-11:20
 Keynote by Jim Lai: The Metamorphosis of Innovations
11:20-11:30
Coffee Break
Step 1 - 勾選你的議程時段（同一時段課程只能勾選一堂）
Track
Track A
Low Power
- ESL to RTL - 		Track B
Low Power
- RTL to FAB - 		Track C
High Performance
Systems Design 		Track D
Achieving Yield for
High Performance
and Low Power
11:30-12:20
Scalable TLM
Platform
Solution for
Low Power Design
[Show Abstract]
Kick Starting
Power Aware
Verification
at the RTL
[Show Abstract]
Xilinx
High Performance
Design Using
FPGAs
[Show Abstract]
Evolving Physical
Verification to
Maximize Yield

[Show Abstract]
12:20-1:30
Lunch and Workshops
1:30-2:20

High-Level
Synthesis:
Synthesizing
Multiple
Clock Domains to
Achieve Low Power

[Show Abstract]
ARM
Delivering High
Performance and
Low Power using
Multiprocessing in
Embedded
Applications
[Show Abstract]
Advanced
Fabrication
for Performance




[Show Abstract]
2D and 3D
Variability
Optimization




[Show Abstract]
2:20-2:30
Coffee Break
2:30-3:20

Mathworks
Rapid FPGA Design
and
Implementation
Using Model-Based
Design
[Show Abstract]
Verification
Strategies for
Mixed-Signal
SoCs


[Show Abstract]
Seamless DDR2
Design




[Show Abstract]
Critical Test
Challenges
at 45nm and
Beyond


[Show Abstract]
3:20-3:30
Coffee Break
3:30-4:20

How to Find
the Bugs Missed
by
Simulation



[Show Abstract]
Multi-Corner-
Multi-Mode P&R
for Timing,
Power, and SI
Closure


[Show Abstract]
Meeting the Low
BER
Requirements of
Today's SERDES
Busses


[Show Abstract]
Common Platform
Common Platform’s
Yield Enhancement
Methodology for
Advanced
Technology
Nodes
[Show Abstract]
4:20-4:40
Lucky Draw and Closing
Contact Information
Step 2 - 請填寫你的個人資料

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